1. Field of the Invention
The present invention relates to a measuring apparatus and a measuring method for measuring an electronic device. More particularly, the present invention relates to a measuring apparatus and a measuring method that measure a jitter transfer function, a bit error rate and jitter tolerance of the electronic device under test.
2. Related Art
Jitter testing is an important item to a serial-deserial communication device. For example, Recommendations and Requirements from International Telecommunication Union and Bellcore ((1) ITU-T, Recommendation G.958: Digital Line Systems Based on the Synchronous Digital Hierarchy for Use on Optical Fibre Cables, November 1994, (2) ITU-T, Recommendation O.172: Jitter and Wander Measuring Equipment for Digital Systems Which are Based on the Synchronous Digital Hierarchy (SDH), March 1999, (3) Bellcore, Generic Requirements GR-1377-Core: SONET OC-192 Transport System Genetic Criteria, December 1998) define
A recovered clock in the recovered data output from the deserializer is compared to a reference clock in phase by being mixed with the reference clock.
The network analyzer measures the jitter transfer function of the deserializer based on phase noise spectra in the digital signal input to the deserializer and phase noise spectra in the recovered data. In a case of measuring the jitter transfer function based on a ratio of the phase noise spectra, however, the phase noises in a region other than the edges of the waveform are included. These phase noises prevent the high-precision measurement of the jitter transfer function.
FIG. 75 explains a case of measuring the jitter transfer function of the deserializer by means of a jitter analyzer. The jitter analyzer generates a clock having a predetermined frequency. A synthesizer modulates this clock. A clock source supplies the clock phase modulated by the sinusoid generated by the synthesizer to a pattern generator. The pattern generator supplies data and clock to the deserializer in accordance with the received clock. The deserializer outputs output data and recovered clock in accordance with the received data. The jitter analyzer receives the input clock and the output recovered clock of the deserializer and samples the input clock and output recovered clock. Note that the band-pass filter eliminates both clock and high frequency jitter components (e.g. see Recommendation G.825).
Next, discuss the measurement problem associated with periodic sampling. The jitter analyzer samples one sample per M periods of the input data. The jitter analyzer also performs each sampling at a timing shifted by a small phase. That is, assuming the period of the input data to be T, the sampling period of the jitter analyzer is MT+TES. Since both the input data measurements of jitter tolerance, jitter generation and jitter transfer function.
Therefore, VLSIs for serial communication have to satisfy the values described in the above specifications. Especially, in the jitter tolerance measurement of a deserializer, (a) a sinusoidal jitter is added to zero-crossings of an input bit stream, then (b) the deserializer samples the serial bit stream at times in the vicinity of decision boundaries (sampling instants) and outputs the serial bit stream as parallel data. (c) one port is connected to a Bit Error Rate Tester and its error rate is calculated. (d) This decision boundary or sampling instant has to be obtained from a recovered clock or a clock extracted from the data stream, in which the zero-crossings have jitter. Thus, it is apparent from the above that the jitter tolerance measurement is one of the most difficult measurements.
First, a conventional measuring apparatus that measures a jitter transfer function of the device under test is described. FIG. 74 explains a case of measuring the jitter transfer function by using a network analyzer. The network analyzer measures the jitter transfer function of the deserializer as the device under test. A signal generator generates a sinewave (reference carrier) having frequency fa supplied to the deserializer. The network analyzer phase modulates the reference carrier by a sinusoid having fb. The modulated carrier clocks a pulse pattern generator. The pulse pattern generator supplies a bit stream to the deserializer.
The deserializer performs serial-parallel conversion for input serial bit stream so as to output the converted data as recovered data of a plurality of bits. The data clock of the pattern is subjected to phase modulation by the sinusoidal wave supplied from the network analyzer. and the output data are periodic waveforms having a period of multiples of T, the result of the sampling are substantially equivalent to that obtained in a case of sampling at a sampling period TES.
The jitter analyzer calculates a ratio of the instantaneous phase spectra of the input data to the instantaneous phase spectra of the output data based on the sampling result and then measures the jitter transfer function of the deserializer based on the thus calculated spectra ratio. However, the jitter analyzer performs the sampling at the sampling period of MT+TES and extracts data equivalent to the data of one period. Thus, it takes much time to measure the jitter transfer function.
Moreover, the jitter analyzer generates the waveform equivalent to one period data from approximately MT/TES samples. Therefore; it is difficult to measure the fluctuation of the period between adjacent edges in the waveform of the input data or the output data. The period fluctuation in the waveform generated by the sampling is a mean value of the period fluctuations between the adjacent edges in M periods of the input data or the output data. Therefore, the jitter analyzer cannot precisely measure the instantaneous phases of the input data and the output data, so that it is difficult to precisely measure the jitter transfer function.
Next, a conventional method for measuring the bit error rate and a conventional method for measuring the jitter tolerance are described. According to an eye-diagram measurement, the performance of the communication device can be tested easily. FIG. 76 shows an eye diagram. The horizontal eye opening provides a peak-to-peak value of the timing jitter, while the vertical eye opening provides noise immunity or a signal-to-noise ratio (Edward A. Lee and David G. Messerschmitt, Digital Communication, 2nd ed., pp. 192, Kluwer Academic Publishers, 1994). In the measurement of the jitter tolerance, however, the zero-crossings of an input bit stream are caused to fluctuate by the timing jitter having a peak-to-peak value of 1 UI(Unit Interval, 1 UI is equal to the bit period Tb) or more. (For example, Recommendation (1) defines 1.5 UIPP.) As a result, the eye-diagram measurement can measure only a closed eye pattern. Therefore, it is found that the eye diagram cannot be applied to the jitter tolerance measurement.
The jitter tolerance measurement is an extension of the bit error rate test. FIG. 77 shows the arrangement of the jitter tolerance measurement of the deserializer. The deserializer performs serial-parallel conversion for the input serial bit stream, and outputs the resultant data as, for example, 16-bit recovered data. The instantaneous phase Δθ[nT] of the input bit stream to the deserializer to be measured is made to fluctuate by the sinusoidal jitter. Please note that T is a data rate. A bit error rate tester delays the output recovered clock with an appropriate time delay so as to obtain the optimum timing instants, and samples the output recovered data at those instants. By comparing the sampled values of the recovered data and expected values corresponding thereto, the bit error rate of the deserialized data is obtained. However, since the output recovered clock is extracted from the serial bit stream in which edges fluctuate, it becomes difficult to sample the output recovered data at the optimum sampling instants under the condition of the large amplitude of the applied jitter. On the other hand, according to the method in which the clock is extracted from the recovered data stream, the bit error rate tester has to include a high-performance clock recovery unit. This is because the clock recovery unit, which has larger jitter tolerance than that of the clock recovery unit included in the deserializer under test, is required for measuring the jitter tolerance of the deserializer under test. In other words, in the jitter tolerance measurement using the bit error rate tester, it is likely to underestimate the jitter tolerance. Therefore, in order to perform the measurement with excellent repeatability, high measurement skill or know-how is required.
Moreover, in the jitter tolerance measurement, while the applied jitter amount is increased with the jitter frequency fJ fixed, the minimum applied jitter amount that causes the occurrence of the bit error is obtained. For example, in order to perform the bit error rate test for a 2.5 Gbps serial communication device by using a pseudo-random binary sequence having a pattern length of 223-1, the test time of 1 sec is required. Therefore, in order to measure the jitter tolerance by changing the jitter amplitude to be supplied 20 times, the test time of 20 sec is required.
Timing degradation of the input bit stream as well as amplitude degradation increases the bit error rate. The timing degradation corresponds to the horizontal eye opening in the eye-diagram measurement, while the amplitude degradation corresponds to the vertical eye opening. Therefore, by measuring the degrees of the timing degradation and amplitude degradation, the bit error rate can be calculated. Please note that the jitter tolerance measurement corresponds to the horizontal eye opening in the eye-diagram measurement. For example, degradation of the amplitude of the received signal of ΔA=10% corresponds to the reduction of the signal-to-noise ratio of 20log10(100−10)/100=0.9 dB. Therefore, the bit error rate increases by 0.9 dB. As for the timing degradation ΔT, the similar calculation can be performed. Please note that the % value of the ratio and the dB value are relative values, not absolute values. In order to obtain an accurate value of the bit error rate, calibration is required. Here, the definition of ΔA and ΔT by J. E. Gersbach (John E. Gersbach, Ilya I. Novof, Joseph K. Lee, “Fast Communication Link Bit Error Rate Estimator,” U.S. Pat. No. 5,418,789, May 23, 1995) is used. The apparatus disclosed in the above patent uses the following equation
  BER  =      10                  -        K                    (                                            Δ              ⁢                                                          ⁢              T                        t                    +                                    Δ              ⁢                                                          ⁢              A                        A                          )            
to calculate an instantaneous bit error rate from ΔA, ΔT, a local clock period T and the maximum value A of the samples at the optimum sampling instants. However, the aforementioned apparatus merely provides a method for estimating the bit error rate by measuring the timing degradation by a Gaussian noise jitter. The apparatus described in the aforementioned patent obtains a histogram of data edges, performs a threshold operation and obtains ΔT. This operation is effective to the Gaussian noise jitter having a single peak. The sinusoidal jitter used in the jitter tolerance test has two peaks at both ends of the distribution. Therefore, ΔT cannot be obtained only by performing the simple threshold operation. Moreover, in the jitter tolerance measurement, the zero-crossings are caused to fluctuate by the timing jitter of 1 UIPP or more. As a result, the histogram has the distribution in which the probability density functions of adjacent edges overlap each other. From such a histogram, it is difficult to obtain ΔT. It is known that this histogram operation cannot secure a sufficient measurement precision unless about 10000 samples or more are obtained (T. J. Yamaguchi, M. Soma, D. Halter, J. Nissen, R. Raina, M. Ishida, and T. Watanabe, “Jitter Measurements of a PowerPC™ Microprocessor Using an Analytic Signal Method,” Proc. IEEE International Test Conference, Atlantic City, N.J., Oct. 3-5, 2000). Therefore, it is hard to reduce the measurement time. Moreover, K in the above equation does not have an ideal value. Therefore, by calibrating the instantaneous bit error rate with the actual bit error rate, the initial value for K has to be given. Also, a correction value ΔK has to be calculated from the difference between the long-term mean value of the instantaneous bit error rate and the actual bit error rate. Therefore, the conventional apparatus is poor in efficiency, requiring the longer test time.